Extra Memory for a PIC Processor - Dynamic Ram

Update Feb2007
Also Works with KM44C256AP-10 256Kx4 Dram
I also found an error in the code, depending on your use of portA, the upper bits need masking when reading the RAM (I wont tell you how long it took me to figure this out). Simply changing the line 'return data' to 'return data & 0x0f' did the trick. In the original code, I had duplicated some of the instructions to allow extra time for the dram to react - I found that these were not neccessary.

I had for a while been toying with the idea of hooking up a RAM chip, Dynamic or Static to a PIC Processor.  The PIC Processors manage to pack a big list of peripheral features into (sometimes) tiny packages but if a large set of data needs to be processed, they can be a little short on RAM.

The idea of hooking up a RAM Chip or other storage chip to the micro's i/o ports is not a new one, and access to the chip would involve calling a routine with the required RAM address.  What was putting me off was that in order to address a big enough memory, quite a few i/o lines would be required.

Recently Elector magazine published an article using an ATTiny2313 processor with a DRAM chip and latch to control an lcd display.  Time, I thought to have a go with a PIC 16F876(a) Processor.

The Elector article used a HY514400 1M by 4Bit dram salvaged from an old sim memory unit.  The author had been able to reduce the number of pins required by multiplexing the data and address lines.

I had hoped to use a 256k by 4 dram from an old video card, but I found that the chips must have been 'reclaimed' and had shorter pins than could be reliably plugged into a breadboard.  The only other drams I had (not soldered onto something) were a couple of TMS4416 16k by 4 drams, one of these was pressed into service.

The data I could find (via google) on the 4416 indicated that as the /cas line was also related to the chip enable function, multiplexing the data and address lines would not work (newer chips may work differently).  I used all of PORT B for the 8 address lines and the lower 4 bits of PORT A for the data lines.  That left /G, /WR, /CAS and /RAS. These were handled by 4 bits from PORT C.  the reason for keeping the Data, Address and Control lines on separate ports was to simplify the amount of bit twidling needed to address and read/write a memory location.

I used Port C0 = /RAS, C1 = /CAS, C2 = /G (enable) and C3 = /WR.

Here is the code I used to read and write the DRAM:-

#define RAM_RAS RC0
#define RAM_CAS RC1
#define RAM_G RC2
#define RAM_WR RC3

void RAM_Write( unsigned int Address, char Data )
{
unsigned char lsb, msb ;
lsb = Address & 0x00FF ;
msb = Address >> 7 ; // was 8 - for 44256 leave it at 8
PORTB = lsb ;
TRISA = 0x00 ; //PortA=Output
PORTA = Data ; // ignoring msb for now!
RAM_RAS = 0 ;
PORTB = msb ; //msb ;

RAM_WR = 0;
RAM_CAS = 0;
RAM_G = 0;
RAM_G = 1;
RAM_WR = 1;
RAM_CAS = 1;
RAM_RAS = 1;
TRISA = 0x0F ;//portA to input

}

char RAM_Read( unsigned int Address )
{
char lsb, msb , data;
int temp2 ;
lsb = Address & 0x00FF ;
msb = Address >> 7 ; // was 8 - for 44256 leave at 8
PORTB = lsb ;
TRISA = 0x0F ; //PortA=input

RAM_RAS = 0 ;
PORTB = msb ; //msb ;
RAM_G = 0;

RAM_WR = 1;
RAM_CAS = 0;
data = PORTA ; // ignoring msb for now!

RAM_G = 1;
RAM_WR = 1;
RAM_CAS = 1;
RAM_RAS = 1;
TRISA = 0x0F ;//portA to input
//return data ; // forgot to mask the upper 4 bits!
return data & 0x0f ;
}

char Mem_Read( unsigned int Address)
{
char c ;
Address = Address << 1;
c=(RAM_Read(Address++)<<4); //get first nibble
c|=RAM_Read(Address++); //get second nibble
return c;

}
void Mem_Write (unsigned int Address, char Data )
{
Address = Address << 1 ;
RAM_Write(Address++,Data >> 4) ;
RAM_Write(Address++,Data) ;

}

Mem_Read and Mem_Write call the RAM_Read and RAM_Write routines twice per byte and allow the 16k by 4 bit DRAM to be accessed as a block 8k by 8.  The upper address bits are ignored so the memory is repeated at 8k blocks throughout the virtual 64k address space.

DRAM memory cells need to be constantly read in order to 'refresh' the data stored.  In order to do this simply, I called a refresh routine when ever the program needed to pause for a serial or other i/o device.  As there were no long loops within the main program this routine accessed the relevant locations often enough to maintain the data.

If your program may go for longer periods without being able to call a similar refresh routine, a timer interupt should be used to ensure that the refresh is performed.

Improvements

As speed was not my main concern, I did not try to optimise the timing of the DRAM access, I just toggled the /ras,/cas,/g and /wr bits in the same order as the data sheet timing diagram suggested and it worked.

Faster Access will be possible by using assembly language and more accurate timing of the control pulses.

To use other DRAMs, it is a good idea to try and find a data sheet. As I found with the 4416 dram, the way the chip treats the column address may vary - in the 4416, bits 1-6 are used (not 0-5 as I had expected).

Also, with a data sheet, it is possible to follow the timing diagrams for the cas, ras, g/oe and rw pins so that they can be toggled in the right order.

Introduction
About the PIC Processor
Programing the PIC
Building Blocks
PIC Test Rig

Connecting an LCD
VoipDeskPhone
VoipDeskPhone the Software
VoipDeskPhone3 Changes for use as an Asterisk Console Phone

Cheap PIC Keypad PoundShop Clock / Alarm = Cheap Keypad

3 State LEDs

Add DRAM to a PIC
PIC Links